The present invention generally relates to phase-locked loop technology.
The phase-locked loop (PLL) was introduced as far back as 1932 by H. de Bellescizi, at that time for synchronous reception of radio signals. Today, the phase-locked loop is found in numerous applications of all modern technologies. It is widely used in all areas of electronics and in different fields of communication.
A phase-locked loop is, in general, a circuit for synchronizing an output signal of the loop with an input reference signal in frequency as well as in phase. It basically consists of the following functional components: an output signal source, a phase detector responsive to the output signal and the reference signal for providing a phase difference representing signal, and a filter circuit which filters the phase difference representing signal. In the synchronized state, also referred to as the locked state or steady state, the phase difference between the loop output signal and the input reference signal is zero, or at least very small, and no frequency offset between the signals exist. If a phase difference builds up, e.g. due to a frequency offset between the loop output signal and the reference signal, or if there is an instantaneous phase jump, a control mechanism in the PLL strives to eliminate the frequency offset and to reduce the phase difference to a minimum. The time required to enter the locked state is called the acquistion time.
The performance evaluation of a PLL is based on acquisition and steady state properties. It is desired to have fast acqusition and low output phase jitter at steady state. The utility of a phase-locked loop is substantially improved if the acquistion time is reduced, a fact well known in the art. The steady state mode should have high rejection of noise disturbances caused by e.g. the internal components of the PLL or environmental changes, which might alter the PLL output, in order to maintain lock of the PLL.
It is the provision of a phase-locked loop having fast acquisition and stability at steady-state to which the present invention is directed.
Many solutions have been proposed to accelerate the acquisition of phase-locked loops and to provide a stable steady state mode. In the following, techniques related to the subject matter of the present invention will be described.
In U.S. Pat. No. 4,419,633 a variable voltage controlled oscillator (VCO) with an associated phase-locked loop is disclosed. The voltage controlled oscillator arrangement comprises a constant frequency reference signal source, a variable counter for normalizing the frequency of the VCO and a coincidence detector comparing the reference frequency to the normalized output frequency and providing an error signal. Further, the VCO-arrangement includes an integrator circuit for integrating the output of the coincidence detector to provide a control signal that adjusts the VCO to change frequency, a lock detector and a fast charge circuit, including two transistors an d two bias resistors, for accelerating the charging process of the integrator circuit when the lock detect or indicates an out-of-lock condition.
U.S. Pat. No. 4,115,745 relates to a phase-lock speed-up circuit comprising a voltage controlled oscillator, a phase detector, reference frequency source and a loop filter connecting the output of the phase detector and the input of the VCO. The loop filter includes an integrator connected in series with a low-pass filter, and stabilizing resistors. Furthermore, the speed-up circuit comprises means for adding direct current to the junction between the stabilizing resistors when the oscillator is out-of-lock.
An interference resistant phase-locked loop is disclosed in U.S. Pat. No. 4,074,207. The phase-locked loop (PLL) has a voltage controlled oscillator (VCO), a phase discriminator for receiving a reference signal and a feedback signal derived from the output signal of the VCO, and a low-pass filter for filtering of the phase difference representing output signal from the discriminator. Moreover, the PLL includes a series connection of a differentiating circuit for the differentiation of the low-pass filter output signal, a limiter for limiting the output signal from the differentiating circuit, and an integrating circuit having an output which produces a control voltage for the VCO. The PLL is insensitive to large phase jumps due to the fact that the limiter is provided to take care of signal magnitudes at the output of the differentiating circuit exceeding the limiting level.
U.S. Pat. No. 4,457,639 relates to a motor control for a DC-motor printer carriage including a phase-locked loop speed control circuit. The motor control has an encoder which detects motor speed, a reference oscillator, a phase comparator for detecting the phase difference between the encoder signal and the reference oscillator output signal, and a switching circuit for voltage to be applied to the motor based upon the phase comparator output. Additionally, the motor control includes a feedback circuit having a low-pass filter for converting the phase comparator output signal into an analog speed signal, and a differentiating circuit for converting the analog speed signal into a quasi-acceleration signal. The feedback circuit effects frequency modulation of the reference oscillator output signal to bring the encoder signal and the reference signal in phase.
A general objective of the present invention is the provision of a phase-locked loop (PLL) having very fast acquisition, and low output phase jitter and stability at steady-state.
In particular, when a PLL is in an out-of-lock condition (i.e. the loop output signal and the input reference signal are not synchronized) it is an object of the invention to reach the locked condition, also referred to as the steady state condition of the PLL, as fast as possible. Moreover, when the PLL is in steady state, the PLL should be able to maintain lock even though subjected to noise disturbances.
In accordance with a general inventive concept, the filter circuit of the phase-locked loop includes a differentiator responsive to the phase difference representing signal from a phase detector in the PLL for providing a differentiated signal, and a filter responsive to both the phase difference representing signal and the differentiated signal to provide a filter output signal. Preferably, the filter is a low-pass filter. In general, the output signal source is controlled by a control signal which is generally based on the filter output signal.
The filter receives a signal representative of the phase difference between the loop output signal and the reference signal, and a signal representative of the rate of change of the phase difference.
The inventive idea is to use the differentiator to speed up the xe2x80x9clock-inxe2x80x9d of the filter. The phase difference representing signal contains information about the phase difference, and the differentiated signal contains information about the time-derivative of the phase difference, i.e. the frequency offset between the reference signal and the loop output signal. By using the information in both the phase difference representing signal and the differentiated signal in the regulation of the phase-locked loop a very fast lock-in is obtained. This is in contrast to prior art techniques which usually focus entirely on the phase difference representing signal. Naturally, it is desired to give the filter the output signal value which it will have at steady state as fast as possible. In accordance with the invention, the differentiator output is connected to the filter (also receiving the phase difference representing signal from the phase detector) and the differentiated signal representative of the frequency offset is pumped into the filter in order to quickly update the output signal of the filter. Thus, the differentiator is not used in the manner described in the aforementioned patents.